Acionyx Inc. Hardware Engineer-Chip Verification (Contract Position) in Lisle, Illinois
Location: Lisle, IL
Local candidates only. Non-local candidates considered if they are willing to relocate at their own expense
Top 3 Required Skills:
Quickly look at and evaluate the tests in place, and with input
from developers here modify/create tests keeping them simple to use.
Working with developers to dial-in the best ways to approach
• Familiarity with PC/Linux tools, QuestaSim, VCS, Quartus, Jenkins, scripting.
• Good understanding of UVM and OOP concepts.
•Familiarity with ClearCase source control.
• Understanding of how much testing is required for FPGAs
Working in Lisle, IL with a small team of FPGA chip developers. Defining,
documenting, creating, and running block and chip level simulations.
Sharing knowledge and ideas on how best to verify and cover the
requirements we are designing to. Many tests exist but need more
attention, enhancement, and organization. Overseeing automating
regression testing on a Linux system. Helping debug the tests and even
parts of the design. Taking over and simplifying some existing UVM based
Responsible for development,
Implementation, and Testing, of complex high-end FPGA designs. A good
deal of verification is already in place including
automated UVM based regression We are looking to better unify the environment while keeping it simple and usable for
Design engineers. This will require working closely with team members to devise the most appropriate testing strategies
for the situation.
Work will include:
· Helping to define and write verification test plans.
· Developing block, multiblock, and possibly chip level simulation test benches.
· Working closely with developers, helping to debug issues.
· Guiding developers on how to most effectively verify their design as it evolves.
· Working with Jenkins, a continuous integration automation server.
· Collecting and tracking test coverage information
Required Skills include:
· Familiarity with FPGA development tools: Quartus, Vivado
· Expert in writing Test Benches
· VHDL, Verilog languages
· Experience with System Verilog, UVM, and Object-Oriented Programming
· Scripting languages, Perl, Tcl, etc.
· Experience with Source Control (ClearCase)
· Linux, Windows, environments
· Simulation tools: Synopsys VCS, Mentor Questa, Aldec Rivera
· Excellent people skills
Skills that would also be useful:
· Matlab experience
· C, C++
*Candidate should have 10 years of experience in this discipline